Author Topic: Software Defined Radio theory  (Read 2615 times)

Anton Janovsky (ZR6AIC)

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Software Defined Radio theory
« on: February 10, 2014, 06:14:59 AM »
Here is some theory that is impotent when you select a SDR or when you design a SDR.

Definition of SDR.

A software-defined radio receiver uses an analog-to-digital converter (ADC) to digitize the analog signal in the receiver as close to the antenna as practical, generally at an intermediate frequency (IF). Once digitized, the signals are filtered, demodulated, and separated into individual channels. Similarly, a software-defined radio transmitter performs coding, modulation, etc. in the digital domain In the final output IF stage, a digital-to-analog converter (DAC) is used to convert the signal back to an analog format for transmission.

Selection of Analog-to-Digital Converters (A/D)

Intermediate Frequency sampling is the process of sampling signals that are not at baseband, i.e., not centered around DC. Depending on the system involved, IF frequencies can be up to several hundred megahertz. Current ADC technology allows sampling of these frequencies with each generation of converters providing improvements in performance. In general, converter performance begins to degrade with increasing input frequency. Converter performance limitations occur in two primary areas. Within the converter, performance is limited by the slew rate of the on-chip analog circuitry. Analog slew rate limitations result in a reduced Spurious Free Dynamic Range (SFDR) performance as the input frequency is increased. The other limitation to IF sampling is jitter on the sample clock (not stable clock). This limitation is due to external factors, so the combination of internal and external factors results in reduced Signal to noise (SNR) performance as the input frequency is increased.

How to Select the Sampling Rate

The selection of sampling rate is also important for ADCs. Fast encode clocks offer the advantage of making analog filtering significantly easier. Given a fixed signal bandwidth, a higher encode rate increases the allowable transition band. This allows lower order filters to be used to reduce cost, or, if higher order filters are still used, greater stop band rejection can potentially be realized.
Another advantage with increasing clock speeds is processing gain. Processing gain is achieved when the signal of interest is oversampled and then digitally filtered. Processing gain occurs when noise outside the band of interest is digitally removed, which results in improved in-band SNR.

Jitter Effect

A significant consideration for any high-speed communications system is the generation of ultralow-jitter,high-speed sampling clocks, and their effect on the data conversion process. Clock jitter is defined as the random variation of the clock position compared to its ideal position with respect to time. Clock jitter has two basic components. One originates from the external clock source; the ADCís clock circuitry creates the other internally. When the position of the clock varies slightly, it alters the position of the sampling point, which in turn samples the input waveform at an imprecise location. This error manifests itself as SNR degradation.

Here is some interesting reading http://www.ti.com/lit/an/slaa407/slaa407.pdf